The present invention relates to a memory device, and more particularly, to a dynamic type memory device.
Memory devices employing insulated gate field effect transistors have been widely used as the most common memories. As is well known, memory devices are generally classified depending upon their modes of access into random access memories (RAMS) and serial access memories. A random access memory is constructed by arraying memory cells in a matrix form and disposing peripheral circuits such as address inverters, decoders, etc. along the periphery of the matrix. In such type of random access memories, a memory cell is formed of a one-transistor and one-capacitor element, and hence the memory matrix can be constructed at a high density. However, in contrast to ease in high density integration of the memory cell matrix, in a peripheral circuit such as, for example, a decoder, the number of input transistors of NOR gates for the respective word lines or the respective digit lines would increase in proportion to the enlargement in memory capacity of the memory cell matrix. In other words, the number of circuit elements necessitated per word line or per digit line in the peripheral circuit increases in proportion to the increase in the memory capacity, and the space on a chip occupied by the entire peripheral circuit that is required for the memory device is rapidly increased. Consequently the proportion of the area occupied by the memory cells on a semiconductor chip is strictly limited, and hence it is difficult to obtain a memory device having a large memory capacity on a small area of a semiconductor chip.
On the other hand, among the serial access memories a shift register is known as a typical one, and in this type of memory, peripheral circuits such as decoders or the like are unnecessary. However, a memory unit of one bit is constructed by cascade connection of two stages of inverters each provided with sampling gate transistors. Accordingly six transistors are necessitated per bit, and thus a very large number of transistors were necessitated in the case of a large memory capacity. In other words it was not practical to realize a serial access memory having a large memory capacity.
Recently, in accordance with the development of the technique of digitally processing signals, such as the technique of digital filters for analog signals, the requirement for a large capacity memory device, especially for a serial access memory having a large memory capacity has been enhanced.